Reliability Determines Submicron Future

The fast growth of consumer electronics, the ubiquitous digitalisation of society and the demand for low-cost applications are driving the need for System-On-Chip (SOC) integration. SOC refers to the consolidation of all printed circuit board functions on a single integrated chip, which typically requires the merging of different types of process technologies (such as CMOS and mixed signal).

With the shift to single-chip solutions integrated on deep submicron CMOS process technologies, reliability concerns emerge. These must be addressed in parallel with the design cycle to ensure no issues arise with the leverage of new process technologies.

RELIABILITY DRIVES CHANGE

The best example of the reliability impact on new process technology introductions was the transition from an aluminium-based interconnect system to a copper-based system at the 0.13µm process technology node. Process, design rule and test programme screening changes were necessary to achieve a reliable, qualifiable and manufacturable solution. This delayed the introduction and ramp to production of the new metal system across the industry.

The main reliability issues related to the vias. Via-stress migration caused voids at the bottom of the vias after a thermal cycle. Stress-induced voiding in copper vias required optimisation of the copper deposition and anneal temperatures. These issues have been resolved and the benefits of 0.13µm products are available.

At the 90nm process node, the transition to a true low-k interlevel dielectric material requires process and design rule optimisation. Low-k materials have a reduced mechanical strength, or modulus, because of their increased porosity, and they have a higher coefficient of thermal expansion compared with their predecessors. Together, these material properties are raising daunting reliability hurdles to low-k integration that have challenged process integration engineers and packaging engineers during the qualification cycle. Solutions to these issues have enabled the qualification and ramp to production of 90nm technology.

Approaching the 65nm and 45nm process nodes, still lower k materials will be required to mitigate the issue of performance loss (due to RC parasitics). This means yet more optimisation will required in this area to allow the leverage of ultra-low-k materials (at k<= 2.5).

Negative Bias Temperature Instability (NBTI) has driven analysis, process and design changes and has prompted many changes in design and process integration. Design teams have had to apply compensation techniques to ensure that design simulations take account of the impact of small PMOS threshold shifts during an application’s lifetime.

TRANSITIONS AHEAD

More materials and process integration transitions will be required if semiconductor technology is to stay aligned with Moore’s Law. It will be the resolution of reliability problems that will determine time to market.

Two of the most significant changes on the transistor horizon will be the introduction of metal gate transistors and high-k gate dielectrics. The transition from the current polysilicon material as the gate electrode to polysilicon and metallic material for the gate electrode is to eliminate the problem of polysilicon depletion as the transistor is scaled beyond the 65nm node. The second major transition will be the introduction of high-k gate dielectric materials to significantly reduce the gate leakage current, or off-current, of the transistor. High-k materials, such as hafnium silicate, have almost two orders of magnitude less leakage than nitrided oxides in use. Again, a set of reliability challenges has to be faced. Fortunately, these are no different to the ones mastered for the standard silicon dioxide materials used for the past 20 years.

BEYOND 90NM

Looking past the 90nm process node, an ever-increasing set of process material changes is emerging. Included in this are changes in the transistor FEOL and interconnect BEOL areas. Reliability challenges will often determine when these materials are leveraged as the baseline for the new process nodes at 65nm or 45nm.