Chipping Away

Back in May 2007, IBM announced its ‘air gap’ chip design using a self-assembly nano approach to create a vacuum between the wires inside a power architecture microprocessor, reducing unwanted capacitance and improving both power performance and efficiency.

IBM also listed nine other major performance improvements that had continued the path of Moore’s Law. These included copper wiring, silicon on insulator and strained silicon, dual core microprocessors, immersion lithography, frozen SiGe chips for 500GHz operation, high-k transistor gates, e-dram tripling embedded memory and 3D chip-stacking with through silicon vias, cutting critical circuit pathways by up to 1,000 times.

CALLING TIME ON MOORE’S LAW

Now IBM fellow, Bernard Meyerson, is calling time on Moore’s Law. He says, “We keep our historical development and leverage that. It is a very different approach from another large chip provider, which deals with vast commodity numbers and rushes to market at each dimensional node that in the past has given better performance.

“That has been true for the past 30 years. Now, any future shrink will cause real problems if you continue to rely on smaller dimensions without additional innovation. There will be no further automatic enhancement of the device; scaling no longer offers performance gain.”

“That now has to come from other ideas, such as wiring and design; the idea that it’s a good thing to get to the next node first without innovating shows a fundamental lack of understanding. Companies hope to cut costs by being first, but don’t ask if it’s necessarily the best long-term solution.

“The reality is that we are well aware that these future nodes have coalesced. Copy exact is applied to a common set of models across the member platform, with such variations as multiple FET or high-end microprocessors merely being tweaks without impacting on the relevance of commonality of overall design.

“On-demand fab manufacturing is unbelievable in how it is developed. It is untouched; no one moves wafers except for robots. Wafers are in a vibration-free environment integrated into machines and are collected by overhead trams which take items to stockers and effect any swap and mix. If you did not know the final specification, you could run the process to the point where all the prior elements were up and running then simply add the relevant software for the processes and shift gears to follow.

“On-demand allows a company to make products based on fast feedback from the market. Automation and sophistication of software allows instant manufacturing and we now do highly automated on demand manufacturing that literally ‘turns on a dime’.”

THE FAB CLUB

Back in June 2007, the semiconductor arm of IBM global engineering dominated the headlines. From a processing viewpoint, it covered opening up the use of silicon-on-insulator (SOI) technology with Cu-45HP for ASIC technology; the release of its Power6 microprocessor using e-dram; the release of three digital and analogue design kits with SiGe BiCMOS 5PAe and 6WL and CMOS 11LP and the issue of ‘on-demand’ manufacturing.

All this detail was almost drowned out in the strategy development partnership alliance news from Freescale, which confirmed January 2007’s intimation that it would cease its research and development manufacturing alliance at France’s STMicroelecronics Crolles2 site and join the IBM alliance of Samsung, Chartered Semiconductor Manufacturing and Infineon.

This involves working on joint semiconductor technology development using CMOS for 45nm and the future 32nm and 22nm developments at IBM’s 300mm research and development fab at Albany Nanotech and Fishkill.

Dr Meyerson, believes that the concept of a ‘fab club’, however, doesn’t do justice to the alliance work where everyone combines technology and joint venture money.

“We have a broad base and a broader history that dates from working with Toshiba and Siemens in the 80s, as well as having excellent relationships with Tokyo Electronic Limited, AMAT, ASML and numerous vendors in this space,” says Meyerson.

He views the current alliance as an ‘ecosystem’ that tracks its development back to the time when IBM – with decades of research and an awesome portfolio of patents – opted to ‘put its family jewels on display and invited other major players’. It is this research and development patents pipeline, also covering manufacturing processes, that extends to products which have helped to create IBM’s powerful ecosystem alliance.

Research and advisory company Gartner is estimating that worldwide semiconductor IP revenue will total $1.8bn in 2006 – a 24.9% increase on 2005 revenues – and $2.7bn by 2010, excluding captive IP property designed and used exclusively by one organisation. The implication for the industry is that it will become more segmented and vendors of highly differentiated IPs will become significant customers of smaller IP blocks, many of whom will be semiconductor vendors.

DATA WINS

The original IBM ‘think’ motto has become ‘data wins’, claims Dr Meyerson, where hard data trumps theory and is the driving force behind the company’s robust 45nm work; which explores a range of areas, such as SiCOH time-dependent dielectric breakdown deterioration of low-k dielectrics in fully integrated interconnects and new air gap chip design developments.

“We have been working not only on 45nm but also on 32nm and 22nm nodes,” explains Dr Meyerson, pointing out that since the silicon roadmap forecasts for those nodes, it makes sense to push research work into those dimensions. Add to that an ecosystem alliance and billions can be saved by the major players who ‘both mitigate risk and are offered an end to working in isolation’.

A slight hint of something to come for IBM in June 2007 involved the chemical supplier BASF and a joint development agreement to work on the electronic materials required in the production of 32nm ICs. The project will work out of IBM’s Fishkill facilities and BASF’s headquarters in Ludwigshafen, Germany. It involves both technology and related materials likely to be commercialised as early as 2010.

In December 2007, the IBM Alliance (AMD, Chartered, Freescale, Infineon, Samsung, Sony and Toshiba) declared that the innovative approach to speed the implementation of the breakthrough material high-k / metal gate in the next generation shrink to 32nm computer chips had been achieved.

Chip size shrinks by up to 50% compared to the previous generation technology and improves a number of other performance specifications – saving about 45% of total power. For microprocessor applications this enables up to 30% higher performance as documented in measurements performed by IBM and its alliance partners at IBM’s East Fishkill, New York semiconductor manufacturing facility.

The implementation of high-k / metal gate will be available to IBM alliance members and their clients by the second half of 2009.