ERM – The Challenges

Included in any essential reading on emerging research devices are the writings of Michael Mayberry, the vice president of technology and manufacturing at Intel. In the world of blogs, gallium arsenide has been ranked fifth out of ten in technology
flops.

“In the 1980s lots of experts thought GaAs would supplant CMOS semiconductor technology in computers. But CMOS’ remarkable scalability has limited gallium arsenide to relatively niche applications,” wrote Steve Tobak, the managing partner of Invisor
Consulting LLC on www.crave.cnet.com on 30 November 2007.

In blogs.intel.com/research, Mayberry opens with the old joke that ‘gallium arsenide is the technology of the future, never the technology of the present’.

But, while ignoring the compound semiconductor’s equally famous jeer at CMOS being an
abbreviation of ‘can’t meet our standards’, Mayberry’s blog goes on to admit that GaAs has about eight times higher mobility compared to silicon and indium antimonide has around (InSb) 50 times higher mobility.

“We’ve shown that you could achieve more than ten times the improvement in power for an InSb device operating at 0.5V compared to the equivalent silicon device (IEDM 2005 presentation),” he notes. These are scaling benefits that Intel and scaleable silicon are determined to acquire.

CHALLENGES FOR IMPROVING POWER

“The sticky point is that we have to figure out how to make these in high volumes… impossible if we were limited to small GaAs wafers as starting material [so] we broke the overall [high-volume] problem into five individual challenges.’ These challenges are:

• Build compound semiconductor devices on silicon substrates
• Find a suitable high-K gate dielectric
• Build a high performance PMOS device to go with the existing NMOS, which is needed for power-efficient CMOS logic
• Build enhancement devices
• Make them small enough to compete with silicon transistor devices

“As of this summer,” Mayberry says, “‘We have achieved success fabricating high performance in devices using two material types – InSb and InGaAs. They are higher performing and use less power than equivalently-sized silicon devices and they perform as well as their counterparts on GaAs wafers. These are the first reports of high performance devices on silicon. This is a major milestone.” It might also mark the removal of GaAs from the flop category.

INTEL PAPERS

It is no surprise then that at the IEDM meeting, Intel presented three papers:

A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning and 100% Pb-free1 packaging describes Intel’s breakthrough 45nm processing technology, with high-k metal gate transistors.

The new gate stack is combined with enhanced third-generation strained silicon to produce n-type metal oxide semiconductor (NMOS) transistors and p-type metal oxide semiconductor (PMOS) transistors with the highest drive currents reported to date.
Logic gate delay has reportedly improved by more than 20% compared to 65nm. The technology is already in high-volume manufacturing.

Reducing variation in advanced logic technologies approaches to process and design manufacturability of nanoscale CMOS shows that process variation is not a barrier to Moore’s Law. Although device dimensions continue to shrink, with each generation Intel is able to co-optimise layout regularity, design innovation and other design-for-manufacturing techniques with process improvements and disruptive inventions to maintain (or improve) process variation across generations.

Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well (QW) transistor on silicon substrate using thin (≤2mm) composite buffer architecture for high-speed and low-voltage (0.5V) logic applications gives a technical view into the latest achievement describing successful fabrication of high performance QW field effect transistors (QWFETs) using III-Vs indium gallium arsenide (InGaAs); III-V QWFETs are promising device candidates for future high-speed, low power digital logic
applications offering very high performance at significantly reduced operating voltage.

Successful fabrication of these devices on silicon wafers would allow seamless integration with more conventional silicon devices, circumventing the inefficiencies of large-diameter III-V substrates.

Devices operate at high performance at only 0.5V,
delivering greater than ten times the power reduction compared to equivalent silicon devices.

“A major problem of making transistor devices smaller is that materials at the nano level behave in different ways, sometimes good and sometimes not so good,” explains Mayberry. “Up to 10nm, there’s a need to compare conventional and smart structures in order to see the quirks. Below the 10nm grail there is a need to do things differently.”

INTERNAL CARBON NANOTUBE (CNT) PROJECT

Among a host of research projects Intel, says Mayberry, has an internal carbon nanotube (CNT) project to characterise and work with the material and an external project with a university on graphene, which can be ‘laid down in big sheets and cut up, but the edges (not a problem with CNT) are tricky. The problem with CNT is the difficulty of control and of structuring its properties; III-Vs materials are promising but still not sufficiently small’.

Acknowledging the sceptics’ doubts on new materials, both inside and outside Intel, Mayberry is happy with current progress on devices and is still looking to extend conventional technology. In the MEMS domain he notes that some projects are being worked on in corporate technology linking sensors to computation, which could hold promise.

Asked where Intel stands on optoelectronics and what part it will play in future generations Mayberry replies, “We have looked at optical clock pulse distribution and consider it unlikely, as our architectural direction will reduce the need to keep a massive system synchronised. We have also looked at interconnects. While bandwidths are high, sizes are still very large versus copper wires. It is more likely that optical will penetrate at longer length scales, box-to-box, first, and migrate over time to chip-to-chip.

Concerning the problem of photonic-electronic integration he says, “The temperature control issue is one we’re looking at.

“Solving it for a specific interface for chip-to-chip is easier than solving it for widely distributed elements. Using active
feedback to adjust optical response is one option.”

The secret of every device generation, Mayberry concludes, is to know how to extend it. Each new generation has ‘a few new ingredients in the sauce, a handful of key features. Currently the high-k metal gate and the quantum well device are among the
things we have worked on to achieve real benefits’.

“Some 80% of work involves ‘tweaking’ from an existing stable generation into the new variability. There’s always a risk in just shrinking things. University professors accuse Intel of being risk adverse,” Mayberry laughs. “But I don’t know if anyone would want to run their car or aircraft on the latest university one-off, research device.