Lithography Steps Up to the Challenge

The pressure is always on the semiconductor industry to print smaller patterns on silicon wafers and to produce the integrated circuits that will power tomorrow’s microchips and electronic devices. This is the realm of lithography, where efforts are under way to reduce the scale at which circuits can be printed.

Optical lithography, or photolithography, is a highly specialised nanolithographic technique used to build integrated circuits (IC) such as DRAMs and microprocessors, which prints finely detailed patterns onto silicon wafers. An image of the desired pattern is projected onto a wafer, coated by the photosensitive ‘resist’.

Bright parts of the image make the resist soluble in a developer liquid, while dark areas remain insoluble. The resist forms a stencilled pattern across the surface, which is permanently transferred onto the wafer surface using, for instance, a chemical etchant.

At all stages there is a drive for innovation – and the need is great. The growing demands by end users for state-of-the-art chips are putting a great deal of pressure on the lithographic process.

Achieving higher resolution means that lines must be printed at much less than 350nm – smaller than the 500nm wavelength of visible light. The complexity of patterns is also increasing, while the need for reliability is as great as ever. Furthermore, working with overlays of multiple patterns at such small scales requires unprecedented levels of accuracy.

“There are many challenges for lithography in the future. Resolution is a big issue, particularly for NAND-flash, critical dimension uniformity (CDU), overlay for DRAM and logic and keeping the cost of ownership reasonable for overlay processes,” says Udo Nothelfer, the vice president of FAB36 for Advanced Micro Devices (AMD).

The company’s FAB36 microprocessor wafer facility in Germany has enabled AMD to increase its capacity by using larger 300mm wafers and highly efficient production techniques.

The facility, which uses AMD’s patented automated precision manufacturing (APM) capabilities, has progressively enabled 90nm and 65nm production shipments over the last two years and represents the peak of the company’s manufacturing and technology innovation. It is, therefore, at the forefront of tackling the many challenges of wafer fabrication.

RESOLUTION SOLUTIONS

Nowhere is the drive to improve resolution more intense than in the production of NAND-flash memory. Producing the next generation of NAND-flash will require a significant step up in fabrication techniques and although new techniques are in development, Nothelfer believes there are few practical options in the short-term and that double patterning (DPT) will be the only technology ready in time.

“NAND-flash has very hard requirements – approximately 32-35nm half-pitch in 2009 – and there are continued delays to the introduction of extreme ultraviolet lithography,” says Nothelfer.

DOUBLE PATTERNING (DPT)

Double, or multiple, patterning (DPT) enables higher density in the wafer fabrication process. DPT can be used as early as the 65nm node, is a primary technique for the 32nm node and can be extended to the 22nm node.

DPT can take many forms, including:

• Double exposure. A sequence of two separate exposures of the same photoresist layer using two different photomasks, commonly used to produce very different patterns in the same layer.
• Spacer mask. A film layer formed on the sidewall of a pre-patterned feature by deposition or reaction of the film on the previous pattern, followed by etching to remove film material on horizontal surfaces, retaining only the material on the sidewalls. In principle, with one lithographic exposure the pitch can be halved indefinitely with a series of spacer and pattern transfer processes.
• Heterogeneous mask. A first exposure is transferred to an underlying hardmask layer, then a second layer of photoresist is coated onto the sample for a second exposure resulting in a set of photoresist features in between hardmask features, which are transferred to the final layer.
• Intermediate pattern accumulation. A sequence of exposures, using different photoresist coating, and etchings produce independent patterns on the same layer. The pattern is a composite of previously etched subpatterns, which can be interwoven to increase pattern density.

EXTREME ULTRAVIOLET LITHOGRAPHY (EUV)

Extreme ultraviolet lithography (EUV) uses the 13.5nm wavelength. As all matter absorbs EUV radiation, EUV lithography must occur in a vacuum and all optical elements – including the photomask – must use defect-free Mo/Si multilayers to reflect light by means of interlayer interference.

Using a much smaller wavelength, EUV promises better resolution but many efforts to develop it are battling with issues around light source, photoresists, defect inspection and EUV interaction with matter require. Currently, the effects of electrons released after absorption negatively impact its resolution capabilities.

EUV promises much but suffers constant delays. This is also likely to affect logic, for which AMD is in a development partnership with IBM through 2011.

“For logic, 35nm half-pitch is targeted for development in early 2009 and production in late 2011.

“It is quite sure that EUV won’t be ready in 2009 and it is still questionable whether it will be production-worthy in 2011, so logic needs to look for DPT solutions as well,” he says.

EUV is a next-generation lithography technology that uses the 13.5nm wavelength and is a significant development from the deep ultraviolet lithography commonly used today, but has many hurdles to overcome before it becomes the standard.

“Overall, EUV today suffers from strong source power and lifetime issues and insufficient resist performance and is missing the capability to deliver and maintain defect-free masks, with the source as the major obstacle. As with DPT, flash-memory makers will be the first that call for EUV, due to its unique resolution needs,” continues Nothelfer.

Another technique in the wings is high-index fluid immersion lithography, which aims to enhance resolution by filling the conventional air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is reduced by a factor equal to the refractive index of the liquid. Current immersion lithography tools using highly purified water can achieve feature sizes below 37nm. Again, however, the industry must wait for the technique to be refined.

“High-index fluid immersion won’t be ready either nor will it give the necessary resolution push for 35nm half-pitch and beyond. In our eyes, it might play a similar role to 157nm-lithography in the past. By that I mean that its success will depend a lot on the progress of its competitors, but this time the competitor will be EUV instead of water immersion,” says Nothelfer.

DEFINING TOMORROW’S LOGIC

AMD’s logic development, which it is pursuing with IBM, continues to investigate techniques including immersion lithography for resolution, use of an ‘ultralow-k’ dielectric to lower chip capacitance and power consumption and an improved version of ‘strained silicon’.

“Short term, logic will move from the historically comfortable k1>0.4 to numbers around 0.35. This is very challenging as, due to its pattern variation, it does not allow very aggressive resolution enhancement techniques today. Applying design rule restrictions will help to overcome these limitations,” says Nothelfer.

“SRAM-printing is already today one of the major challenges and will become even more difficult with every node. Larger and larger memories – L2, L3 – have to be integrated into the chip. The classical 6T-SRAM-cell consumes a lot of space and proper cell engineering is the key for success. But SRAM scaling becomes more and more difficult due to device variability at smaller dimensions.”

From a lithographic perspective, three major challenges emerge. The first is to achieve extremely good gate critical dimension (CD) control. Secondly, contact imaging must be further explored, looking in particular at common depth of focus (DOF). Lastly, the industry must innovate to improve contact-to-gate overlay.

“Due to design style, contacts are hardly amenable for pitch-splitting techniques. For single exposure, the available DOF goes below the current tool and process capabilities, thus smart ways to optimise contact layout and illumination schemes, and minimise all key contributors to focus variation, will be the major challenge,” believes Nothelfer.

Optical proximity correction (OPC) aims to improve photolithography by compensating for image errors due, for instance, to refraction. Common applications are line width differences between features in regions of different density and line end shortening. These have been shown to improve the cost profile of photomask fabrication, in part by significantly increasing the data capacity of the photomask layout.

“If logic moves to low k1, the quality of OPC will be crucial for success. New disciplines like ‘computational lithography’ and new OPC-styles, such as dense OPC, emerge. OPC engineers are trying to optimise the whole exposure system – illumination, mask, lens and wafer. This is an iterative process where we will have an optimised mask layout and the best illumination scheme at the end,” says Nothelfer.

FIGHTING ON ALL FRONTS

The implications of each innovation reach many levels of the fabrication process. OPC, for instance, has a significant bearing on mask development.

“Very complex OPC, including the use of sub-resolution features, puts a lot of pressure to the mask business due to the huge increase data volume,” says Nothelfer.

“This can have a tremendous impact on the mask data-preparation-process and the mask write time. Mask inspection will be a further challenge for the mask industry, in particular due to the presence of very small scatter bars. These developments will lead to an increasing portion of mask costs on the overall cost of ownership. Up to 40% of lithographic costs per layer can be consumed by the mask,” he says.

Use of DPT means mask registration needs go far beyond those of single mask patterning.

Nothelfer notes, however, that there are promising improvements in the pipeline – including mask-to-mask overlay, writer dedication and grid-manipulation – that might meet the industry’s requirements. With DPT, critical dimension uniformity (CDU) is a critical issue and µP-gate is the major driver.

“Using DPT, CD-control at the final pattern will be influenced by multiple error sources – exposure one and two, etch one and two and overlay. Even if the targeted aggressive overlay numbers below three nanometres are achieved, the attainable final numbers might be good enough for flash but they are too high for logic,” says Nothelfer.

New techniques like spacer and double exposure techniques are what he feels are needed to not only deliver better CDU, but also to make the technique more cost-effective. DRAM has the hardest requirements in terms of overlay though logic is not far behind.

“DPT requires very tight overlay numbers – three nanometres – between the two corresponding masks. This includes exposure tool, etch, mask and metrology impact. Historically, DRAM was always the driver for tight overlay.

“However, due to the aforementioned SRAM shrink needs, the needs of logic – in particular for contact-to-gate overlay – are following DRAM very closely with single digit requirements coming pretty soon,” says Nothelfer. “Tool dedication, chuck dedication, non-linear correction and in-die overlay schemes will be unavoidable.”

CONTROLLING COSTS

Though there is a strong tide of innovation in semiconductor fabrication, each breakthrough is not judged solely by the performance gains that it enables, but also on its cost profile.

Preciously, some experts have expressed doubts over the ability of traditional optical lithography techniques to remain cost-effective below 30nm, which has fuelled the drive for next-generation lithographic techniques. Nothelfer feels the cost issue will become increasingly important in the short to medium-term.

“Although exposure tool prices have increased significantly with every generation, the throughput and the number of resolved pixels per area has increased more strongly. Thus, the lithography cost per transistor has gone down exponentially with each generation,” he notes.

“With the advent of DPT, however, this trend will now stop for the first time in history. Although EUV will be even more expensive than immersion tools, it promises to deliver better cost of ownership compared to DPT – up to 30% less. EUV will be a single exposure with relatively inexpensive masks and little in the way of OPC,” he says.

The potential rewards from enhanced lithographic techniques are great indeed, but the industry will have to wait for many of them to bear fruit.